DK-DEV-5SGXEA7N【PDF 80/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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4-10

HSSI Outputs

SV51005

2014.01.10

HSSI Outputs

Every three HSSI outputs generate a group of six PCLKs to the core.

Related Information

High-Speed I/O Design Guidelines for Stratix V Devices on page 6-8

Provides more information about DPA and HSSI outputs.

PLL Clock Outputs

The Stratix V PLL clock outputs can drive both GCLK and RCLK networks.

Clock Input Pin Connections to GCLK and RCLK Networks

Table 4-2: Dedicated Clock Input Pin Connectivity to the GCLK Networks for Stratix V Devices

Clock Resources

GCLK[0,1,2,3]

GCLK[4,5,6,7]

GCLK[8,9,10,11]

GCLK[12,13,14,15]

CLK (p/n Pins)

CLK[0,1,2,3,20,21,22,23]

CLK[4,5,6,7]

CLK[8,9,10,11,12,13,14,15]

CLK[16,17,18,19]

Table 4-3: Dedicated Clock Input Pin Connectivity to the RCLK Networks for Stratix V Devices

A given clock input pin can drive two adjacent RCLK networks to create a dual-regional clock network.

Clock Resources

RCLK[58,59,60,61,62,63,64,68,85,89]

RCLK[58,59,60,61,62,63,65,69,86,90]

RCLK[58,59,60,61,62,63,66,70,87,91]

RCLK[58,59,60,61,62,63,67,88]

RCLK[20,24,28,30,34,38]

RCLK[21,25,29,31,35,39]

RCLK[22,26,32,36]

RCLK[23,27,33,37]

RCLK[52,53,54,55,56,57,71,75,78,82]

RCLK[52,53,54,55,56,57,72,76,79,83]

RCLK[52,53,54,55,56,57,73,77,80,84]

RCLK[52,53,54,55,56,57,74,81]

RCLK[46,47,48,49,50,51,71,75,78,82]

RCLK[46,47,48,49,50,51,72,76,79,83]

RCLK[46,47,48,49,50,51,73,77,80,84]

Altera Corporation

CLK (p/n Pins)

CLK[0]

CLK[1]

CLK[2]

CLK[3]

CLK[4]

CLK[5]

CLK[6]

CLK[7]

CLK[8]

CLK[9]

CLK[10]

CLK[11]

CLK[12]

CLK[13]

CLK[14]

Clock Networks and PLLs in Stratix V Devices

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